ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
Preliminary Technical Data
ADSP-21469/ADSP-21469W
Table 6. Pin List (Continued)
Name
DDR2_CKE
DDR2_CS3-0
DDR2_DATA15-0
DDR2_DM1-0
Type
O/T
O/T
I/O/T
O/T
DDR2_DQS1-0
DDR2_DQS1-0
DDR2_RAS
DDR2_WE
I/O/T (Differential)
O/T
O/T
DDR2_CLK0,
DDR2_CLK0,
DDR2_CLK1,
DDR2_CLK1
DDR2_ODT
AMI_MS0–1
O/T (Differential)
O/T
O/T
FLAG[0]/IRQ0
FLAG[1]/IRQ1
FLAG[2]/IRQ2/
AMI_MS2
FLAG[3]/TIMEX P/
AMI_MS3
LDAT07–0
LDAT17-0
LCLK0
LCLK1
LACK0
LACK1
THD_P
THD_M
TDI
I/O
I/O
I/O
I/O
I/0
I/O
I/O
I
O
I (pu)
TDO
O /T
TMS
I (pu)
State
During
and After
LVTTL SSTL18 Reset Description
3
High-Z/ DDR2 Clock Enable Output to DDR2. Active high signal. Connect to DDR2
Driven low CKE signal.
3
High-Z/ DDR2 Chip Select. All commands are masked when DDR2_CS3-0 is driven
Driven high. DDR2_CS3-0 are decoded emory address lines. Each DDR2_CS3-0lines
high
select the corresponding bank.
3
High-Z DDR2 Data In/Out. Connect to corresponding DDR2_DATA pins.
3
High-Z/ DDR2 Input Data Mask. Mask for the DDR2 write data if driven high. Sampled
Driven on both edges of DDR2_DQS at DDR2 side. DM0 corresponds to DDR2_DATA
high
7–0 and DM1 corresponds to DDR2_DATA 15–8.
3
High-Z Data Strobe. Output with Write Data. Input with Read Data. DQS0 corre-
sponds to DDR2_DATA 7–0 and DQS1 corresponds to DDR2_DATA 15–8.
3
High-Z/ DDR2 Row Address Strobe. Connect to DDR2_RAS pin, in conjunction with
Driven other DDR2 command pins, defines the operation for the DDR2 to perform.
high
3
High-Z/ DDR2 Write Enable. Connect to DDR2_WE pin, in conjunction with other
Driven DDR2 command pins, defines the operation for the DDR2 to perform
high
3
High-Z/ DDR2 Clock. Free running, minimum frequency not guaranteed during reset.
driven low
3
3
3
3
3
3
3
3
3
3
3
3
High-Z/ DDR2 On Die Termination. ODT pin when driven high (along with other
Driven low requirements) enables the DDR2 termination resistances.
High-Z Memory Select Lines 0–1. These lines are asserted (low) as chip selects for
the corresponding banks of external memory on the AMI interface. The MS1-
0 lines are decoded memory address lines that change at the same time as the
other address lines. When no external memory access is occurring the MS1-0
lines are inactive; they are active however when a conditional memory access
instruction is executed, whether or not the condition is true.
The MS1 pin can be used in EPORT/FLASH boot mode. For more information,
see the ADSP-2146x SHARC Processor Hardware Reference.
High-Z FLAG0/Interrupt Request0.
High-Z FLAG1/Interrupt Request1.
High-Z FLAG2/Interrupt Request2/Async Memory Select2.
High-Z FLAG3/Timer Expired/Async Memory Select3.
High-Z Link Port Data (Link Ports 0-1).
High-Z Link Port Clock (Link Ports 0–1).
High-Z Link Port Acknowledge (Link Port 0-1).
High-Z
Thermal Diode Anode
Thermal Diode Cathode
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI
has a fixed internal pull-up resistor1, 2.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a
fixed internal pull-up resistor1, 2.
Rev. PrB | Page 13 of 56 | November 2008
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