ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
ADSP-21469/ADSP-21469W
Preliminary Technical Data
Table 6. Pin List (Continued)
State
During
and After
Name
TCK
Type
I (pu)
LVTTL SSTL18 Reset
3
Description
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be
asserted (pulsed low) after power-up or held low for proper operation of the
TRST
I (pu)
3
ADSP-21469.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-
21469. TRST has a fixed internal pull-up resistor1, 2.
EMU
O/T (pu)
3
High-Z Emulation Status. Must be connected to the ADSP-21469 Analog Devices
CLK_CFG1–0
I
3
DSP Tools product line of JTAG emulators target board connector only. EMU
has a fixed internal pull-up resistor1, 2.
Core to CLKIN Ratio Control. These pins set the start up clock frequency. See
Table 9 for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL
multiplier and divider in the PMCTL register at any time after the core comes
BOOT_CFG2–0
I
3
out of reset.
Boot Configuration Select. These pins select the boot mode for the proces-
sor. The BOOTCFG pins must be valid before reset is asserted. See Table 8 for
RESET
I (pu)
3
a description of the boot modes.
Processor Reset. Resets the ADSP-21469 to a known state. Upon deassertion,
there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core
begins program execution from the hardware reset vector address. The RESET
XTAL
O
3
input must be asserted (low) at power-up.
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an
CLKIN
I
3
external crystal.
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21469 clock
input. It configures the ADSP-21469 to use either its internal clock generator
or an external clock source. Connecting the necessary components to CLKIN
and XTAL enables the internal clock generator. Connecting the external clock
to CLKIN while leaving XTAL unconnected configures the ADSP-21469 to use
the external clock source such as an external clock oscillator. CLKIN may not
CLKOUT/
I/O (pu)
3
be halted, changed, or operated below the specified frequency.
Clock Out/Reset Out/Running Reset In. The functionality can be switched
RESETOUT/
between the PLL output clock and reset out by setting Bit 12 of the PMCTL
RUNRSTIN
register. The default is reset out. This pin also has a third function as RUNRSTIN.
The functionality of which is enabled by setting bit 0 of the RUNRSTCTL
register. For more information, see the ADSP-2146x SHARC Processor Hardware
BR6-1
I/O
RPBA
I
ID2-0
I
Reference.
3
High-Z/ Bus request. Bus request pins for external DDR2 bus arbitration.
Driven low
3
Rotating priority bus arbitration.
3
Chip ID
1 Pull-up/pull-down resistor can not be enabled/disabled and the value of the pull-up/pull-down resistor cannot be programmed.
2 Range of fixed pull-up resistor can be between 26k-63kΩ. Range of fixed pull-down resistor can be between 31k-85kΩ.
Rev. PrB | Page 14 of 56 | November 2008
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