ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
Preliminary Technical Data
TIMING SPECIFICATIONS
The ADSP-21469’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, and serial ports. During reset, program the ratio between
the processor’s internal clock frequency and external (CLKIN)
clock frequency with the CLKCFG1–0 pins (see Table 9 on
ADSP-21469/ADSP-21469W
Page 15). To determine switching frequencies for the serial
ports, divide down the internal clock, using the programmable
divider control of each port (DIVx for the serial ports).
Figure 3 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the
ADSP-2136x SHARC Processor Programming Reference.
PMCTL
CLK_CFGx/
PMCTL
LINKPORT
CLOCK
DIVIDER
LCLK
CLKIN
XTAL
BUF
PLLI
CLKIN CLK
DIVIDER
PMCTL
RESET
DELAY OF
4096 CLKIN
CYCLES
RESETOUT
PLL
LOOP
FILTER
VCO
PLL
MULTIPLIER
CLK_CFGx/PMCTL
CLKOUT
PLL
DIVIDER
PMCTL
DDR2
DIVIDER
CCLK
CLK_CFGx/
PMCTL
DDR2_CLK
CLK_CFGx/
PMCTL
DIVIDE PCLK
BY 2
PMCTL
PCLK
CCLK
BUF
RESETOUT/
CLKOUT
CORERST
Figure 3. Core Clock and System Clock Relationship to CLKIN
The ADSP-21469’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the sys-
tem clock (CLKIN) signal and the processor’s internal clock.
Core clock frequency can be calculated as:
fCCLK = (2 × PLLM × fINPUT) ÷ (2 × PLLN)
Note that in the user application, the PLL multiplier value
should be selected in such a way that the VCO frequency falls in
between 160 MHz and 800 MHz. The VCO frequency is calcu-
lated as follows:
fVCO = 2 × PLLM × fINPUT
where:
fVCO is the VCO frequency
PLLM is the multiplier value programmed
fINPUT is the input frequency to the PLL in MHz.
fINPUT = CLKIN when the input divider is disabled
fINPUT = CLKIN ÷ 2 when the input divider is enabled
Note the definitions of various clock periods shown in Table 12
which are a function of CLKIN and the appropriate ratio con-
trol shown in Table 11.
Table 11. CLKOUT and CCLK Clock Generation Operation
Timing
Requirements
CLKIN
CCLK
Description
Input Clock
Core Clock
Calculation
1/tCK
1/tCCLK
Rev. PrB | Page 19 of 56 | November 2008
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