ADSP-21477 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21477' PDF : 76 Pages View PDF
ADSP-21477/ADSP-21478/ADSP-21479
CLKIN
XTAL
BUF
CLKIN fINPUT
DIVIDER
PMCTL
(INDIV)
PLL
LOOP
FILTER
fVCO
PLL
VCO
DIVIDER
fCCLK
PMCTL
(SDCKR)
CCLK
SDRAM
DIVIDER
CLK_CFGx/
PMCTL (2 × PLLM)
PMCTL
(PLLD)
fVCO ÷ (2 × PLLM)
PMCTL
(PLLBP)
DIVIDE PCLK
BY 2
PMCTL
(PLLBP)
PCLK
CCLK
SDCLK
RESET
DELAY OF
4096 CLKIN
CYCLES
RESETOUT
CLKOUT (TEST ONLY)*
*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS fINPUT.
THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.
Figure 5. Core Clock and System Clock Relationship to CLKIN
BUF
RESETOUT
CORESRST
Rev. C | Page 26 of 76 | July 2013
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