ADSP-BF522BBCZ-3A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF522BBCZ-3A' PDF : 88 Pages View PDF
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Table 44. Serial Ports—Internal Clock for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
VDDEXT
1.8V Nominal
Parameter
Min
Max
Timing Requirements
tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx1
11.0
tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx1
–1.5
tSDRI Receive Data Setup Before RSCLKx1
11.0
tHDRI Receive Data Hold After RSCLKx1
–1.5
Switching Characteristics
tSCLKIW TSCLKx/RSCLKx Width
10.0
tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
3.0
tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 –2.0
tDDTI Transmit Data Delay After TSCLKx2
3.0
tHDTI Transmit Data Hold After TSCLKx2
–1.8
1 Referenced to sample edge.
2 Referenced to drive edge.
VDDEXT
2.5 V or 3.3V Nominal
Min
Max
Unit
9.6
ns
–1.5
ns
9.6
ns
–1.5
ns
8.0
ns
3.0
ns
–1.0
ns
3.0
ns
–1.5
ns
Table 45. Serial Ports—Internal Clock for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
Parameter
Timing Requirements
tSFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
tHFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx1
tSDRI
Receive Data Setup Before RSCLKx1
tHDRI
Receive Data Hold After RSCLKx1
Switching Characteristics
tSCLKIW
tDFSI
TSCLKx/RSCLKx Width
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)2
tHOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)2
tDDTI
Transmit Data Delay After TSCLKx2
tHDTI
Transmit Data Hold After TSCLKx2
1 Referenced to sample edge.
2 Referenced to drive edge.
VDDEXT
1.8V Nominal
Min
Max
11.0
–1.5
11.0
–1.5
4.5
3.0
–1.0
3.0
–1.8
VDDEXT
2.5 V or 3.3V Nominal
Min
Max
Unit
9.6
ns
–1.5
ns
9.6
ns
–1.5
ns
4.5
ns
3.0
ns
–1.0
ns
3.0
ns
–1.5
ns
Rev. D | Page 54 of 88 | July 2013
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