ADSP-BF522BBCZ-3A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF522BBCZ-3A' PDF : 88 Pages View PDF
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 49 and Figure 29 describe SPI port slave operations.
Table 49. Serial Peripheral Interface (SPI) Port—Slave Timing
ADSP-BF522/ADSP-BF524/
ADSP-BF526
ADSP-BF523/ADSP-BF525/
ADSP-BF527
VDDEXT
1.8V Nominal
VDDEXT
2.5 V or 3.3V
Nominal
VDDEXT
1.8V Nominal
VDDEXT
2.5 V or 3.3V
Nominal
Parameter
Min
Max Min
Max Min
Max Min
Max Unit
Timing Requirements
tSPICHS
tSPICLS
tSPICLK
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
4×
tSCLK – 1.5
4 × tSCLK – 1.5
4×
tSCLK – 1.5
4 × tSCLK – 1.5
ns
tHDS
Last SCK Edge to SPISS Not Asserted
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
tSPITDS Sequential Transfer Delay
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
tSDSCI SPISS Assertion to First SCK Edge
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
tSSPID Data Input Valid to SCK Edge (Data Input 1.6
1.6
1.6
1.6
ns
Setup)
tHSPID SCK Sampling Edge to Data Input Invalid 2.0
1.6
1.6
1.6
ns
Switching Characteristics
tDSOE SPISS Assertion to Data Out Active
0
12.0 0
10.3 0
12.0 0
10.3 ns
tDSDHI
tDDSPID
tHDSPID
SPISS Deassertion to Data High Impedance 0
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold) 0
11.0 0
10
0
8.5 0
10
0
8.5 0
10
0
8 ns
10 ns
ns
SPIxSS
(INPUT)
SPIxSCK
(INPUT)
SPIxMISO
(OUTPUT)
CPHA = 1
SPIxMOSI
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tDSOE
tDDSPID
tHDSPID
tSSPID
tHSPID
tDSOE
SPIxMISO
(OUTPUT)
CPHA = 0
SPIxMOSI
(INPUT)
tHDSPID
tSPICLK
tDDSPID
tHDS
tSPITDS
tDSDHI
tDDSPID
tSSPID
tDSDHI
tHSPID
Figure 29. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. D | Page 59 of 88 | July 2013
Share Link: 
