ADSP-BF523C View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF523C' PDF : 44 Pages View PDF
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
SPI Timing
Table 18. SPI Timing
Parameter
Test Conditions1 Min Max Unit
tDSU
CSDA to CSCL setup time
20
ns
tDHO
CSCL to CSDA hold time
tSCH
CSCL pulse width high
tSCL
CSCL pulse width low
tSCS
CSCL rising edge to CSB rising edge
tCSS
CSB rising to CSCL rising
tCSH
CSB pulse width high
tCSL
CSB pulse width low
tPS
Pulse width of spikes to be suppressed
20
ns
20
ns
20
ns
60
ns
20
ns
20
ns
20
ns
0 5 ns
1 AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25°C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 × fS unless otherwise stated.
CSB
tCSL
tCSH
CSCL
tSCH tSCL
tSCS
tCSS
CSDA
tDSU
tDHO
Figure 19. SPI Timing
Rev. A | Page 26 of 36 | March 2010
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