ADSP-BF523C View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF523C' PDF : 44 Pages View PDF
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Digital Audio Interface Master Mode Timing
Table 20. Digital Audio Interface Master Mode Timing
Parameter
Test Conditions1 Min
tDST
DACDAT setup time to CODEC_BCLK rising edge
30
tDHT
tDL
tDDA
tBCLKR
tBCLKF
tBCLKDS
DACDAT hold time to CODEC_BCLK rising edge
ADCLRC/DACLRC propagation delay from CODEC_BCLK falling edge
ADCDAT propagation delay from CODEC_BCLK falling edge
CODEC_BCLK rising time (10 pF load)
CODEC_BCLK falling time (10 pF load)
CODEC_BCLK duty cycle (normal and USB mode)
10
10
10
45:55
1 AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25°C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 × fS unless otherwise stated.
Max
10
10
55:45
Unit
ns
ns
ns
ns
ns
ns
CODEC_BCLK
DACLRC/
ADCLRC
DACDAT
ADCDAT
tDL
tDST
tDHT
tDDA
Figure 21. Digital Audio Interface Master Mode Timing
Rev. A | Page 28 of 36 | March 2010
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