ADSP-BF539WBBCZ-5A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539WBBCZ-5A' PDF : 68 Pages View PDF
ADSP-BF539/ADSP-BF539F
Preliminary Technical Data
PIN DESCRIPTIONS
ADSP-BF539/ADSP-BF539F processor pin definitions are listed
in Table 10.
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins, which are driven high.
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pull-ups or pull-downs, as noted
in the table. In order to maintain maximum functionality and
reduce package size and pin count, some pins have dual, multi-
plexed functionality. In cases where pin functionality is
reconfigurable, the default state is shown in plain text, while
alternate functionality is shown in italics.
Table 10. Pin Descriptions
Pin Name
Memory Interface
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
BR
BG
BGH
Asynchronous Memory Control
AMS3–0
ARDY
AOE
ARE
AWE
Flash Control
FCE
FRESET
Synchronous Memory Control
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
Timers
TMR0
TMR1/PPI_FS1
TMR2/PPI_FS2
Type Function
Driver
Type1 Pull-Up/Down Requirement
O Address Bus for Async/Sync Access
A
I/O Data Bus for Async/Sync Access
A
O Byte Enables/Data Masks for Async/Sync Access A
I
Bus Request
O Bus Grant
A
O Bus Grant Hang
A
Pull high when not used
O Bank Select
I
Hardware Ready Control
O Output Enable
O Read Enable
O Write Enable
A
Pull low when not used.
A
A
A
I
Flash Enable (ADSP-BF539F only)
I
Flash Reset (ADSP-BF539F only)
O Row Address Strobe
O Column Address Strobe
O Write Enable
O Clock Enable
O Clock Output
O A10 Pin
O Bank Select
Leave unconnected or pull low for
ADSP-BF539
Leave unconnected or pull low for
ADSP-BF539
A
A
A
A
A
B
A
A
I/O Timer 0
C
I/O Timer 1/PPI Frame Sync1
C
I/O Timer 2/PPI Frame Sync2
C
Rev. PrF | Page 22 of 68 | September 2006
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