ADSP-BF539WBBCZ-5A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF539WBBCZ-5A' PDF : 68 Pages View PDF
ADSP-BF539/ADSP-BF539F
TIMING SPECIFICATIONS
Table 13 describes the timing requirements for the ADSP-
BF539/ADSP-BF539F processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock, system clock and Voltage Controlled Oscillator
Table 13. Core Clock Requirements
Parameter
tCCLK Core Cycle Period (VDDINT= 1.14 V minimum)
tCCLK Core Cycle Period (VDDINT= 1.045 V minimum)
tCCLK Core Cycle Period (VDDINT= 0.95 V minimum)
1 See Operating Conditions on Page 27.
Table 14. Phase Locked Loop Operating Conditions
Parameter
fVCO
Voltage Controlled Oscillator (VCO) Frequency
Table 15. Maximum SCLK Conditions
Parameter1
fSCLK
CLKOUT/SCLK Frequency (VDDINT ≥ 1.14 V)
fSCLK
CLKOUT/SCLK Frequency (VDDINT < 1.14 V)
1 tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK.
Preliminary Technical Data
(VCO) operating frequencies, as described in Absolute Maxi-
mum Ratings on Page 29. Table 14 describes Phase Locked
Loop operating conditions.
TJUNCTION = 125°C
Min
Max
2.50
3.00
3.39
All1 Other TJUNCTION
Min
Max
2.00
2.75
2.50
Unit
ns
ns
ns
Minimum
Maximum
Unit
50
Max CCLK
MHz
VDDEXT = 3.3 V
133
100
VDDEXT = 2.7 V
133
100
Unit
MHz
MHz
Rev. PrF | Page 30 of 68 | September 2006
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