ADUC7033BSTZ-88 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADUC7033BSTZ-88' PDF : 140 Pages View PDF
ADuC7033
COMPLETE MMR LISTING
In the following MMR tables, addresses are listed in hex code. Access types include R for read, W for write, and RW for read and write.
Table 19. IRQ Address Base = 0xFFFF0000
Address Name
Access
Byte Type Default Value
0x0000 IRQSTA 4
R
0x00000000
0x0004 IRQSIG1 4
R
0x0008 IRQEN
4
RW
0x00000000
0x000C IRQCLR 4
W
0x0010 SWICFG 4
W
0x0100 FIQSTA 4
R
0x0104 FIQSIG1 4
R
0x00000000
0x0108 FIQEN
4
RW
0x00000000
0x010C FIQCLR 4
W
Description
Active IRQ Source. See the Interrupt System section and Table 50.
Current State of All IRQ Sources (Enabled and Disabled). See the Interrupt
System section and Table 50.
Enabled IRQ Sources. See the Interrupt System section and Table 50.
MMR to Disable IRQ Sources. See the Interrupt System section and Table 50.
Software Interrupt Configuration MMR. See the Programmed Interrupts
section and Table 51.
Active IRQ Source. See the Interrupt System section and Table 50.
Current State of All IRQ Sources (Enabled and Disabled). See the Interrupt
System section and Table 50.
Enabled IRQ Sources. See the Interrupt System section and Table 50.
MMR to Disable IRQ Sources. See the Interrupt System section and Table 50.
1 Depends on the level on the external interrupt pins (GPIO_0, GPIO_5, GPIO_7, and GPIO_8).
Table 20. System Control Address Base = 0xFFFF0200
Address Name
Access
Byte Type Default Value
0x0220 SYSMAP0 1
RW
N/A
0x0230 RSTSTA 1
RW
N/A
0x0234 RSTCLR 1
W
N/A
0x0238 SYSSER01 4
RW
N/A
0x023C SYSSER11 4
RW
N/A
0x0240 SYSCHK1 4
RW
N/A
1 Updated by kernel.
Description
REMAP Control Register. See the Remap Operation section and Table 10.
Reset Status MMR. See the Reset section and Table 11 and Table 12.
RSTSTA Clear MMR. See the Reset section and Table 11 and Table 12.
System Serial Number 0. See the Part Identification section and Table 99 for
details.
System Serial Number 1. See the Part Identification section and Table 100 for
details.
Kernel Checksum. See the System Kernel Checksum section.
Table 21. Timer Address Base = 0xFFFF0300
Address Name
Access
Byte Type
Default Value
0x0300 T0LD
2
RW
0x0000
0x0304 T0VAL0 2
R
0x0000
0x0308 T0VAL1 4
R
0x00000000
0x030C T0CON
4
RW
0x00000000
0x0310 T0CLRI
1
W
N/A
0x0314 T0CAP
2
RW
0x0000
0x0320 T1LD
4
RW
0x0324 T1VAL
4
R
0x0328 T1CON
4
RW
0x032C T1CLRI
1
W
0x00000000
0xFFFFFFFF
0x01000000
N/A
0x0330 T1CAP
4
R
0x00000000
Description
Timer0 Load Register. See the Timer0—Lifetime Timer and Timer0 Load
Registers sections.
Timer0 Value Register 0. See the Timer0—Lifetime Timer and Timer0 Value
Registers (T0VAL0/T0VAL1) sections.
Timer0 Value Register 1. See the Timer0—Lifetime Timer and Timer0 Value
Registers (T0VAL0/T0VAL1) sections.
Timer0 Control MMR. See the Timer0—Lifetime Timer and Timer0 Control
Register sections.
Timer0 Interrupt Clear Register. See the Timer0—Lifetime Timer and Timer0
Clear Register sections.
Timer0 Capture Register. See the Timer0—Lifetime Timer and Timer0 Capture
Register sections.
Timer1 Load Register. See the Timer1 and Timer1 Load Registers sections.
Timer1 Value Register. See the Timer1 and Timer1 Value Register sections.
Timer1 Control MMR. See the Timer1 and Timer1 Control Register sections.
Timer1 Interrupt Clear Register. See the Timer1 and Timer1 Clear Register
sections.
Timer1 Capture Register. See the Timer1 and Timer1 Capture Register sections.
Rev. B | Page 37 of 140
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