ADUC7033BSTZ-88 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADUC7033BSTZ-88' PDF : 140 Pages View PDF
ADuC7033
Table 27. STI Base Address = 0xFFFF0880
Address Name
Access
Byte Type
0x0880 STIKEY0
4
W
0x0884 STICON
2
RW
Default Value
N/A
0x0000
0x0888 STIKEY1
4
W
N/A
0x088C STIDAT0
2
RW
0x0000
0x0890 STIDAT1
2
RW
0x0000
0x0894 STIDAT2
2
RW
0x0000
Description
STICON Prewrite Key. See the Serial Test Interface Key0 Register section.
Serial Test Interface Control MMR. See the Serial Test Interface Control
Register section.
STICON Postwrite Key. See the Serial Test Interface Key1 Register section
and Table 91.
STI Data MMR 0. See the Serial Test Interface Data0 Register section.
STI Data MMR 1. See the Serial Test Interface Data1 Register section.
STI Data MMR 2. See the Serial Test Interface Data2 Register section.
Table 28. SPI Base Address = 0xFFFF0A00
Address Name
Access
Byte Type
0x0A00 SPISTA
1
R
0x0A04 SPIRX
1
R
0x0A08 SPITX
1
W
0x0A0C SPIDIV
1
RW
0x0A10 SPICON
2
RW
Default Value
0x00
0x00
0x1B
0x0000
Description
SPI Status MMR. See the SPI Status Register section and Table 90.
SPI Receive MMR. See the SPI Receive Register section.
SPI Transmit MMR. See the SPI Transmit Register section.
SPI Baud Rate Select MMR. See the SPI Divider Register section.
SPI Control MMR. See the SPI Control Register section and Table 89.
Table 29. GPIO Base Address = 0xFFFF0D00
Address Name
Access
Byte Type Default Value
0x0D00 GP0CON
4
RW
0x11100000
0x0D04 GP1CON
4
RW
0x10000000
0x0D08 GP2CON
4
RW
0x01000000
0x0D20 GP0DAT1
4
RW
0x000000XX
0x0D24 GP0SET
4
W
0x0D28 GP0CLR
4
W
0x0D30 GP1DAT1
4
RW
0x000000XX
0x0D34 GP1SET
4
W
0x0D38 GP1CLR
4
W
0x0D40 GP2DAT1
4
RW
0x000000XX
0x0D44 GP2SET
4
W
0x0D48 GP2CLR
4
W
1 Depends on the level on the external GPIO pins.
Description
GPIO Port0 Control MMR. See the GPIO Port0 Control Register section
and Table 59.
GPIO Port1 Control MMR. See the GPIO Port1 Control Register section
and Table 60.
GPIO Port2 Control MMR. See the GPIO Port2 Control Register section
and Table 61.
GPIO Port0 Data Control MMR. See the GPIO Port0 Data Register section
and Table 62.
GPIO Port0 Data Set MMR. See the GPIO Port0 Set Register section and
Table 65.
GPIO Port0 Data Clear MMR. See the GPIO Port0 Clear Register section
and Table 68.
GPIO Port1 Data Control MMR. See the GPIO Port1 Data Register section
and Table 63.
GPIO Port1 Data Set MMR. See the GPIO Port1 Set Register section and
Table 66.
GPIO Port1 Data Clear MMR. See the GPIO Port1 Clear Register section
and Table 69.
GPIO Port2 Data Control MMR. See the GPIO Port2 Data Register section
and Table 64.
GPIO Port2 Data Set MMR. See the GPIO Port2 Set Register section and
Table 67.
GPIO Port2 Data Clear MMR. See the GPIO Port2 Clear Register section
and Table 70.
Rev. B | Page 41 of 140
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