ADUC7033BSTZ-88 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADUC7033BSTZ-88' PDF : 140 Pages View PDF
ADuC7033
16-BIT, Σ-Δ ANALOG-TO-DIGITAL CONVERTERS
The ADuC7033 incorporates two independent sigma-delta
The Σ-Δ modulator converts the sampled input signal into a
(Σ-Δ) analog-to-digital converters (ADCs), namely: the current
digital pulse train whose duty cycle contains the digital infor-
channel ADC (I-ADC) and the voltage/temperature channel ADC
mation. A modified Sinc3, programmable, low-pass filter is
(V/T-ADC). These precision measurement channels integrate
then employed to decimate the modulator output data stream
on-chip buffering, a programmable gain amplifier, 16-bit, Σ-Δ
to give a valid 16-bit data conversion result at programmable
modulators, and digital filtering for precise measurement of
output rates from 4 Hz to 8 kHz in normal mode, and 1 Hz to
current, voltage, and temperature variables in 12 V automotive
2 kHz in low power mode.
battery systems.
The I-ADC also incorporates counter, comparator, and
CURRENT CHANNEL ADC (I-ADC)
The I-ADC converts battery current sensed through an external
100 μΩ shunt resistor. On-chip programmable gain means that
the I-ADC can be configured to accommodate battery current
levels from ±1 A to ±1500 A.
accumulator logic. This allows the I-ADC result to generate an
interrupt after a predefined number of conversions have elapsed
or if the I-ADC result exceeds a programmable threshold value.
A fast ADC overrange feature is also supported. When enabled,
a 32-bit accumulator automatically sums the 16-bit I-ADC results.
As shown in Figure 17, the I-ADC employs a Σ-Δ conversion
technique to realize 16 bits of no missing codes performance.
The time to a first valid (fully settled) result on the current
channel is three ADC conversion cycles with chop mode turned
off and two ADC conversion cycles with chop mode turned on.
Rev. B | Page 43 of 140
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