ADUC7033BSTZ-88 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADUC7033BSTZ-88' PDF : 140 Pages View PDF
ADuC7033
Table 40. ADC Conversion Rates and Settling Times
Chop
Enabled
Averaging Factor
Running
Average
No
No
No
No
No
Yes
No
Yes
No
No
Yes
Yes
Yes
N/A
N/A
fADC
512,000
[SF + 1]× 64
512,000
[SF + 1]× 64
512,000
[SF + 1]× 64 ×[3 + AF]
512,000
[SF + 1]× 64 ×[3 + AF]
512,000
[SF +1]×64 ×[3 + AF]+ 3
1 An additional time of approximately 60 μs per ADC is required before the first ADC is available.
Table 41. Allowable Combinations of SF and AF
SF
0 to 31
32 to 63
64 to 127
0
1 to 7
Yes
Yes
Yes
Yes
Yes
No
8 to 63
Yes
No
No
AF Range
tSETTLING 1
3
f ADC
4
f ADC
1
f ADC
2
f ADC
2
f ADC
Rev. B | Page 54 of 140
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