AMD
Write Register 7
D7 D6 D5 D4 D3 D2 D1 D0
SYNC7
SYNC5
SYNC5
SYNC11
0
SYNC6
SYNC4
SYNC14
SYNC10
1
SYNC5
SYNC3
SYNC13
SYNC9
1
SYNC4
SYNC2
SYNC12
SYNC8
1
SYNC3
SYNC1
SYNC11
SYNC7
1
SYNC2
SYNC0
SYNC10
SYNC6
1
SYNC1
1
SYNC9
SYNC5
1
SYNC0
1
SYNC8
SYNC4
0
Monosync 8 Bits
Monosync 8 Bits
Bisync 16 Bits
Bisync 12 Bits
SDLC
Write Register 7′
D7 D6 D5 D4 D3 D2 D1 D0
Auto Tx Flag
Auto EOM Latch Reset
Auto RTS
TxD Pulled High in SDLC NRZI Mode
Fast DTR/REQ Mode
CRC Check Bytes Completely Received
Extended Read Enable
Must Be Set to 0
Write Register 9
Write Register 11
D7 D6 D5 D4 D3 D2 D1 D0
00
01
10
11
VIS
NV
DLC
MIE
Status High/Status Low
Interrupt Masking
No Reset
without INTACK*
Channel Reset B
Channel Reset A
Force Hardware Reset
*Added Enhancement
D7 D6 D5 D4 D3 D2 D1 D0
0 0 TRxC Out = XTAL Output
0 1 TRxC Out = Transmit Clock
1 0 TRxC Out = BR Generator Output
1 1 TRxC Out = DPLL Output
TRxC O/I
0 0 Transmit Clock = RTxC Pin
0 1 Transmit Clock = TRxC Pin
1 0 Transmit Clock = BR Generator Output
1 1 Transmit Clock = DPLL Output
0 0 Receive Clock = RTxC Pin
0 1 Receive Clock = TRxC Pin
1 0 Receive Clock = BR Generator Output
1 1 Receive Clock = DPLL Output
RTxC XTAL/No XTAL
10216F-13
Figure 9. Write Register Bit Functions (continued)
22
Am85C30