AM85C30-8PC View Datasheet(PDF) - Advanced Micro Devices
Part Name
Description
MFG CO.
'AM85C30-8PC' PDF : 68 Pages View PDF
AMD
Interrupt Acknowledge Cycle Timing
NO TAG illustrates Interrupt Acknowledge cycle timing.
Between the time INTACK goes Low and the falling
edge of RD, the internal and external IEI/IEO daisy
chains settle. If there is an interrupt pending in the ESCC
and IEI is High when RD falls, the Acknowledge cycle is
intended for the SCC. In this case, the ESCC may be
programmed to respond to RD Low by placing its inter-
rupt vector on D7–D0 ; it then sets the appropriate Inter-
rupt-Under-Service latch internally.
A/B, D/C
INTACK
CE
WR
D7 –D0
Address Valid
Data Valid
Figure 10. Read Cycle Timing
10216F-14
A/B, D/C
INTACK
CE
WR
D7 –D0
Address Valid
Data Valid
Figure 11. Write Cycle Timing
10216F-15
INTACK
RD
D7 –D0
Vector
Figure 12. Interrupt Acknowledge Cycle Timing
10216F-16
24
Am85C30
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