APU0071-002WE-TY View Datasheet(PDF) - Anpec Electronics
Part Name
Description
MFG CO.
'APU0071-002WE-TY' PDF : 28 Pages View PDF
APU0071
1-8. Set DDRAM Address
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code 0
0
1 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address to AC. This instruction allows the MPU to access DDRAM data.
When DDRAM addressing mode 1 (A = 0) , DDRAM address is from “00H” to “0FH”.
In DDRAM addressing mode 2 (A = 1) , DDRAM address range of the 1st 16 character is “00H” to “0FH”,
and DDRAM address range of the 2nd 16 character is “40H” to “4FH”.
1-9. Read Busy Flag & Address
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code 0
0 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 DDRAM
MSB
LSB
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code 0
0 BF ∗
∗ AC4 AC3 AC2 AC1 AC0 CGRAM
MSB
LSB
" ∗ " : Don't care
This instruction shows whether APU0071 is in internal operation or not. If the resultant BF is High, The
internal operation is in progress and should wait until BF to be Low, which by then the next instruction can
be performed. In the instruction you can read also the value of address counter.
1-10. Write data to RAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code 1
0 D7 D6 D5 D4 D3 D2 D1 D0 DDRAM
MSB
LSB
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code 1
0
∗
∗
∗ D4 D3 D2 D1 D0 CGRAM
MSB
LSB
" ∗ " : Don't care
Write binary 8/5 bit data to DDRAM / CGRAM. The selection of RAM from DDRAM / CGRAM is set by the
previous address set instruction (DDRAM address set, CGRAM address set) . After writing operation, the
address is automatically increased / decreased by 1, according to the entry mode.
Copyright ANPEC Electronics Corp.
14
Rev. A.07 - FEB., 2002
www.anpec.com.tw
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