APU0071-002WE-TY View Datasheet(PDF) - Anpec Electronics
Part Name
Description
MFG CO.
'APU0071-002WE-TY' PDF : 28 Pages View PDF
APU0071
1-11. Read data from RAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code 1
0 D7 D6 D5 D4 D3 D2 D1 D0 DDRAM
MSB
LSB
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code 1
0
∗
∗
∗ D4 D3 D2 D1 D0 CGRAM
MSB
LSB
" ∗ " : Don't care
Read BINARY 8 / 5 bit from DDRAM / CGRAM. The selection of RAM is set by the previous address set
instruction. If the address set instruction of RAM is not performed before this instruction, data that was
read first becomes invalid, as the direction of AC is not determined. If RAM data is read several times
without RAM address set instruction before read operation, the correct RAM data can be detained from
the second, but the first data would be incorrect, as there is no time margin to transfer the RAM data. In
case of DDRAM reading operation, the cursor shift instruction plays the same role as DDRAM address set
instruction also transfers RAM data to output data register. After read operation address counter is auto-
matically increased / decreased by 1 according to the entry mode. After CGRAM read operation is, the
display shift may not be executed correctly.
∗ In case of RAM write operation, AC is increased / decreased by 1 like read operation (after this
operation) . In this time, AC indicates the next address position, but only the previous data can be read by
read instruction.
2. INTERFACE with MPU
2-1. Interface with 8-bit MPU
With 8-bit interfacing data length transfer is performed at a time through 8 ports, from DB0 to DB7.
Example of timing sequence is shown below.
Copyright ANPEC Electronics Corp.
15
Rev. A.07 - FEB., 2002
www.anpec.com.tw
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