AT45DB021B-CC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT45DB021B-CC' PDF : 32 Pages View PDF
AT45DB021B
9. AC Waveforms
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low
when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high
when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup
and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows tim-
ing that is compatible with SPI Mode 3.
9.1 Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
CS
SCK
tCSS
tWH
tWL
tCSH
tV
HIGH IMPEDANCE
SO
tHO
VALID OUT
tSU
tH
SI
VALID IN
tCS
tDIS
HIGH IMPEDANCE
9.2 Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
CS
SCK
SO
SI
tCSS
tWL
tWH
tV
HIGH Z
tSU
tHO
VALID OUT
tH
VALID IN
tCSH
tCS
tDIS
HIGH IMPEDANCE
15
1937J–DFLSH–9/05
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