AT73C501 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT73C501' PDF : 28 Pages View PDF
Output Operations
The data output by AT73C500 can be divided into three
categories: data to external processor, status information
and impulse outputs. AT73C500 reads mode information,
and in mode 3 and 4, also calibration data via external bus.
For the I/O operation, two 8-bit buses are allocated.
The same eight data lines are reserved both for the
impulse outputs and for the processor interface. The sepa-
ration is done with two address pins. When communicating
with the microprocessor, address 1 (pin ADDR1) is acti-
vated (high). Impulses are output combined with a high
level of address 0 (ADDR0). For status information sepa-
rate 8-bit bus is reserved. The table below describes the
use of the two buses of AT73C500.
Data bits
B0 - B7
B8 - B15
B0 - B7
B12 - B14
Bus
Data Bus
Status Bus
Data Bus
Status Bus
Address
ADDR0
ADDR0
ADDR1
ADDRx
Mode
Output
Output
Input/
Output
Input
Usage
Impulse
Outputs
Status
Information
Processor
Interface
Mode
Inputs
For status and impulse outputs, external latches are
needed to store the information while buses are used for
other tasks. In most cases, the data bus of AT73C500 and
processor I/O bus can be connected directly with each
other. The data transfer is controlled by handshake signals,
ADDR1, RD/WR, STROBE and BRDY. One of the status
outputs DATRDY (B9, ADDR0) can be used as an interrupt
signal. Interrupt can be also generated from the handshake
lines.
In most meters, only some of the I/O operations of
AT73C500 are needed. If a meter contains a separate pro-
cessor, status outputs of AT73C500 are typically not used
since the processor will anyway track the status information
supplied by AT73C500. Often only one or two of the
impulse outputs are wired to the test LED or electrome-
chanical counter.
Data Transfer to External Microprocessor
The calculation results of AT73C500 are transferred to pro-
cessor via 8-bit parallel bus. During normal operation, the
information transfer is divided into six packages which are
written in 200ms intervals after the calculations over ten
line frequency cycles have been completed. There is a time
interval of one line cycle between each individual data
package. The first four bytes of a package contain synchro-
nization, mode and status information, and the rest 12
bytes are reserved for the actual measurement results. The
contents of the six data packages are as follows:
Byte
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data
Sync LS
Sync MS
Mode
Status
REG0
REG0
REG0
REG0
REG1
REG1
REG1
REG1
REG2
REG2
REG2
REG2
PACKAGE 0
Order
Meaning
Single byte Synchronization
Single byte Synchronization
Single byte Mode information
Single byte Status information
LS byte
Active power, phase 1
(LS+1) byte Active power, phase 1
(LS+2) byte Active power, phase 1
MS byte Active power, phase 1
LS byte
Active power, phase 2
(LS+1) byte Active power, phase 2
(LS+2) byte Active power, phase 2
MS byte Active power, phase 2
LS byte Active power, phase 3
(LS+1) byte Active power, phase 3
(LS+2) byte Active power, phase 3
MS byte Active power, phase 3
Byte
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data
Sync LS
Sync MS
Mode
Status
REG3
REG3
REG3
REG3
REG4
REG4
REG4
REG4
REG5
REG5
REG5
REG5
PACKAGE 1
Order
Meaning
Single byte Synchronization
Single byte Synchronization
Single byte Mode information
Single byte Status information
LS byte Reactive power, phase 1
(LS+1) byte Reactive power, phase 1
(LS+2) byte Reactive power, phase 1
MS byte Reactive power, phase 1
LS byte Reactive power, phase 2
(LS+1) byte Reactive power, phase 2
(LS+2) byte Reactive power, phase 2
MS byte Reactive power, phase 2
LS byte Reactive power, phase 3
(LS+1) byte Reactive power, phase 3
(LS+2) byte Reactive power, phase 3
MS byte Reactive power, phase 3
12
AT73C500
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