AT73C501 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT73C501' PDF : 28 Pages View PDF
AT73C500
The six data packages arrive as follows:
Figure 9. Data transfer to processor in six packages
20 ms
200ms = 655360 clocks @ 3.2768 MHz
DATRDY
Pack Pack Pack Pack
0
1
2
3
Pack Pack Pack Pack Pack Pack
4
5
0
1
2
3
LINE PERIOD
1
2
3
4
5
6
7
8
9 10 1
2
3
4
5
In normal mode, the Sync LS byte indicates the number of
data package which will follow (value 0...5). There are also
two special situations indicated by this byte. Value six of
Sync LS byte means that the processor is expected to sup-
ply calibration data to AT73C500. Value seven is written by
AT73C500 in case power interruption is detected and bill-
ing information needs to be transferred to microprocessor.
In this case the processor knows that both packages 3 and
4 will follow one after each other as shown in Figure 10.
Content of Sync LS byte is described in the following table.
Bits 3-7 of the Sync LS byte are not used.
Sync LS byte
Data
B7 - B3 B2 B1 B0 package Mode
XXXXX 0 0 0
0
Normal operation,
Data output
XXXXX 0 0 1
1
Normal operation,
Data output
XXXXX 0 1 0
2
Normal operation,
Data output
XXXXX 0 1 1
3
Normal operation,
Data output
XXXXX 1 0 0
4
Normal operation,
Data output
XXXXX 1 0 1
Normal operation,
5
Data output
XXXXX 1 1
0
(none)
DSP waiting for
calibration data
PFAIL active,
X X X X X 1 1 1 3 and 4 billing information
to be transferred
The Sync MS byte contains a unique 8-bit data, 80H. It can
be used as a synchronization byte by the external control-
ler.
The mode byte contains the following information:
Figure 10. Meaning of bits in mode byte
Mode byte
B7 B6 B5 B4 B3 B2 B1 B0
Not used
State of MODE
input pins of the
DSP
The contents of the status byte equals the content of the
external Status bus as described in the section “Status
Information” on page 17.
In the beginning of I/O operation, AT73C500 writes a high
pulse to B9 pin of the Status bus (ADDR0). This pin can be
externally latched to lengthen the pulse over the whole out-
put operation. It can be used to generate a data ready
(DATRDY) interrupt to processor.
Figure 11 shows the timing of one data package. In nomi-
nal conditions, it takes 200 clock cycles to transfer all 16
bytes. A high pulse (DATRDY) is written to bit B9
(SMBUS1) of Status bus 11 clocks before the first byte is
available and low pulse 12 clocks after the last byte has
been sent.
15
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