AT73C501 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT73C501' PDF : 28 Pages View PDF
Figure 11. Contents of a data package
45 clock cycles
200 clock cycles
143 clock cycles
LATCHED
DATRDY
CLK
STROBE
Sync LS
Sync MS
Synchronisation data
Mode
Status
Status data
AT73C500 offers some time for the processor to analyze
the synchronization, status and mode information before
starting to supply the measurement results. The 12 mea-
surement bytes are written on every 11th clock period.
Four handshake signals are provided, ADDR1, RD/WR,
STROBE and BRDY, for interfacing with the microproces-
sor. ADDR1 is always taken high when AT73C500 is either
Figure 12. Handshake signals of the DSP
Data 1
Data 2
Data 11
Measurement data, 12 bytes
Data 12
writing to µP bus or reading the bus contents. When used
with slow peripheral, the BRDY input of AT73C500 can be
used to hold the device in write mode until the processor
has finished reading the bus. However, the total length of
one data package should always be less than 300 clock
cycles of AT73C500. Longer I/O periods may result errone-
ous measurement results.
CLK
SDLY
DATA
FROM DSP
DDLY
BRS
BRDY
SH
STROBE
ASU
ADDR1
RWSU
RWH
RD/WR
Following the falling edge of BRDY, the data can be
strobed into the µP by the rising edge of the STROBE sig-
nal. If the microprocessor is able to read data continuously,
BRDY can be kept constantly low. Also BRDY should be
low whenever DATRDY is inactive allowing AT73C500
freely use its buses.
To avoid conflicts, the processor should always keep its
bus in tri-state mode, unless it is used to write calibration
coefficients to AT73C500.
16
AT73C500
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