DC Parameters for Low
Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 5.5V ; F = 0 to 30 MHz.
TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7 V to 5.5V ; F = 0 to 30 MHz.
Table 23. DC Parameters for Low Voltage
Symbol Parameter
Min
Typ
Max
Unit
Test Conditions
VIL
VIH
VIH1
VOL
VOL1
VOH
VOH1
IIL
ILI
ITL
RRST
CIO
Input Low Voltage
Input High Voltage except XTAL1, RST
Input High Voltage, XTAL1, RST
Output Low Voltage, ports 1, 2, 3 (6)
Output Low Voltage, port 0, ALE, PSEN (6)
Output High Voltage, ports 1, 2, 3
Output High Voltage, port 0, ALE, PSEN
Logical 0 Input Current ports 1, 2 and 3
Input Leakage Current
Logical 1 to 0 Transition Current, ports 1, 2, 3
RST Pulldown Resistor
Capacitance of I/O Buffer
IPD
Power Down Current
ICC
under
RESET
Power Supply Current Maximum values, X1
mode: (7)
-0.5
0.2 VCC + 0.9
0.7 VCC
0.9 VCC
0.9 VCC
50
90 (5)
20 (5)
10 (5)
0.2 VCC - 0.1
V
VCC + 0.5
V
VCC + 0.5
V
0.45
V
0.45
V
V
V
-50
µA
±10
µA
-650
µA
200
kΩ
10
pF
50
30
µA
1 + 0.2 Freq
(MHz)
at12MHz 3.4
mA
at16MHz 4.2
IOL = 0.8 mA(4)
IOL = 1.6 mA(4)
IOH = -10 µA
IOH = -40 µA
Vin = 0.45V
0.45V < Vin < VCC
Vin = 2.0 V
Fc = 1 MHz
TA = 25°C
VCC = 2.0 V to 5.5V(3)
VCC = 2.0 V to 3.3 V(3)
VCC = 3.3 V(1)
ICC
Power Supply Current Maximum values, X1
operating mode: (7)
1 + 0.3 Freq
(MHz)
at12MHz 4.6
at16MHz 5.8
mA
VCC = 3.3 V(8)
ICC
Power Supply Current Maximum values, X1
idle
mode: (7)
0.15 Freq
(MHz) + 0.2
at12MHz 2
mA
at16MHz 2.6
VCC = 3.3 V(2)
Notes:
1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 17.), VIL =
VSS + 0.5V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used..
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC -
0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 15.).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-
ure 16.).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
38 TS8xCx2X2
4184I–8051–02/08