AT91M40400 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91M40400' PDF : 116 Pages View PDF
AT91M40400
Synchronous Receiver
When configured for synchronous operation (SYNC = 1),
the receiver samples the RXD signal on each rising edge of
the Baud Rate clock. If a low level is detected, it is consid-
ered as a start. Data bits, parity bit and stop bit are sampled
and the receiver waits for the next start bit. See example in
Figure 38.
Figure 38. Synchronous Mode: Character Reception
Example: 8-bit, parity enabled 1 stop
SCK
RXD
Sampling
D0 D1 D2 D3 D4 D5 D6 D7
Stop Bit
True Start Detection
Parity Bit
Receiver Ready
When a complete character is received, it is transferred to
the US_RHR and the RXRDY status bit in US_CSR is set.
If US_RHR has not been read since the last transfer, the
OVRE status bit in US_CSR is set.
Parity Error
Each time a character is received, the receiver calculates
the parity of the received data bits, in accordance with the
field PAR in US_MR. It then compares the result with the
received parity bit. If different, the parity error bit PARE in
US_CSR is set.
Framing Error
If a character is received with a stop bit at low level and
with at least one data bit at high level, a framing error is
generated. This sets FRAME in US_CSR.
Time-Out
This function allows an idle condition on the RXD line to be
detected. The maximum delay for which the USART should
wait for a new character to arrive while the RXD line is inac-
tive (high level) is programmed in US_RTOR (Receiver
Time-out). When this register is set to 0, no time-out is
detected. Otherwise, the receiver waits for a first character
and then initializes a counter which is decremented at each
bit period and reloaded at each byte reception. When the
counter reaches 0, the TIMEOUT bit in US_CSR is set. The
user can restart the wait for a first character with the
STTTO (Start Time-Out) bit in US_CR
Calculation of time-out duration:
Duration = Value x 4 x Bit period
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