AT91SAM9263 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91SAM9263' PDF : 52 Pages View PDF
z Boot Mode Select
z Non-volatile Boot Memory can be internal or external
z Selection is made by BMS pin sampled at reset
z Remap Command
z Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
z Allows Handling of Dynamic Exception Vectors
7.3 Matrix Masters
The Bus Matrix of the AT91SAM9263 manages nine masters, thus each master can perform an access concurrently with
others to an available slave peripheral or memory.
Each master has its own decoder, which is defined specifically for each master.
Table 7-1.
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
Master 6
Master 7
Master 8
List of Bus Matrix Masters
OHCI USB Host Controller
Image Sensor Interface
Two D Graphic Controller
DMA Controller
Ethernet MAC
LCD Controller
Peripheral DMA Controller
ARM926 Data
ARM926™ Instruction
7.4 Matrix Slaves
The Bus Matrix of the AT91SAM9263 manages eight slaves. Each slave has its own arbiter, thus allowing to program a
different arbitration per slave.
The LCD Controller, the DMA Controller, the USB OTG and the USB Host have a user interface mapped as a slave on
the Matrix. They share the same layer, as programming them does not require a high bandwidth.
Table 7-2.
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
List of Bus Matrix Slaves
Internal ROM
Internal 80 Kbyte SRAM
Internal 16 Kbyte SRAM
LCD Controller User Interface
DMA Controller User Interface
USB Host User Interface
External Bus Interface 0
External Bus Interface 1
Peripheral Bridge
SAM9263 [Summary] 16
6249IS–ATARM–28-Jan-13
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