7.8 Debug and Test Features
z ARM926 Real-time In-circuit Emulator
z Two real-time Watchpoint Units
z Two Independent Registers: Debug Control Register and Debug Status Register
z Test Access Port Accessible through JTAG Protocol
z Debug Communications Channel
z Debug Unit
z Two-pin UART
z Debug Communication Channel Interrupt Handling
z Chip ID Register
z Embedded Trace Macrocell: ETM9™
z Medium+ Level Implementation
z Half-rate Clock Mode
z Four Pairs of Address Comparators
z Two Data Comparators
z Eight Memory Map Decoder Inputs
z Two 16-bit Counters
z One 3-stage Sequencer
z One 45-byte FIFO
z IEEE1149.1 JTAG Boundary-scan on All Digital Pins
SAM9263 [Summary] 19
6249IS–ATARM–28-Jan-13