z Register Interface to address, data, status and control registers
z DMA Interface, operating as a master on the Memory Controller
z Interrupt generation to signal receive and transmit completion
z 28-byte transmit and 28-byte receive FIFOs
z Automatic pad and CRC generation on transmitted frames
z Address checking logic to recognize four 48-bit addresses
z Support promiscuous mode where all valid frames are copied to memory
z Support physical layer management through MDIO interface control of alarm and update time/calendar data in
10.5.15 Image Sensor Interface
z ITU-R BT. 601/656 8-bit mode external interface support
z Support for ITU-R BT.656-4 SAV and EAV synchronization
z Vertical and horizontal resolutions up to 2048 x 2048
z Preview Path up to 640*480
z Support for packed data formatting for YCbCr 4:2:2 formats
z Preview scaler to generate smaller size image
z Programmable frame capture rate
SAM9263 [Summary] 43
6249IS–ATARM–28-Jan-13