3.3.20.2 Silent Mode
A falling edge at EN when TXD is high switches the IC into silent mode. The TXD signal has to be logic high during the mode
select window (see Figure 3-3). The transmission path is disabled in silent mode. The overall supply current from VBatt is a
combination of the IVSsi 57µA plus the VCC regulator output current IVCC.
The internal slave termination between the LIN pin and the VS pin is disabled in silent mode, only a weak pull-up current
(typically 10µA) between the LIN pin and the VS pin is present. silent mode can be activated independently from the actual
level on the LIN, WAKE, or KL_15 pins.
If an under voltage condition occurs, NRES is switched to low, and the IC changes its state to fail-safe mode.
A voltage lower than the LIN pre_wake detection VLINL at the LIN pin activates the internal LIN receiver and switches on the
internal slave termination between the LIN pin and the VS pin.
Figure 3-3. Switch to Silent Mode
Normal Mode
Silent Mode
EN
TXD
NRES
Mode select window
td = 3.2μs
VCC
LIN
Delay time silent mode
td_sleep = maximum 20μs
LIN switches directly to recessive mode
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