ATA6612C View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATA6612C
Atmel Corporation
'ATA6612C' PDF : 312 Pages View PDF
5.6.1.5 ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise
generated by digital circuitry. This gives more accurate ADC conversion results.
5.6.2
Clock Sources
The device has the following clock source options, selectable by flash fuse bits as shown below. The clock from the selected
source is input to the AVR® clock generator, and routed to the appropriate modules.
Table 5-4. Device Clocking Options Select(1)
Note:
Device Clocking Option
Low power crystal oscillator
Full swing crystal oscillator
Low frequency crystal oscillator
Internal 128kHz RC oscillator
Calibrated internal RC oscillator
External clock
Reserved
1. For all fuses “1” means unprogrammed while “0” means programmed.
CKSEL3..0
1111 - 1000
0111 - 0110
0101 - 0100
0011
0010
0000
0001
5.6.2.1 Default Clock Source
The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed, resulting in 1.0MHz
system clock. The startup time is set to maximum and time-out period enabled. (CKSEL = “0010”, SUT = “10”,
CKDIV8 = “0”). The default setting ensures that all users can make their desired clock source setting using any available
programming interface.
5.6.2.2 Clock Startup Sequence
Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles before it can be
considered stable.
To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after the device reset is released by
all other reset sources. The Section 5.8 “System Control and Reset” on page 60 describes the start conditions for the internal
reset. The delay (tTOUT) is timed from the watchdog oscillator and the number of cycles in the delay is set by the SUTx and
CKSELx fuse bits. The selectable delays are shown in Table 5-5. The frequency of the watchdog oscillator is voltage
dependent as shown in Section 6.4 “Register Summary” on page 291.
Table 5-5. Number of Watchdog Oscillator Cycles
Typ Time-out (VCC = 5.0V)
0ms
4.1ms
65ms
Typ Time-out (VCC = 3.0V)
0ms
4.3ms
69ms
Number of Cycles
0
4K (4,096)
8K (8,192)
Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum VCC. The delay will not monitor the
actual voltage and it will be required to select a delay longer than the VCC rise time. If this is not possible, an internal or
external brown-out detection circuit should be used. A BOD circuit will ensure sufficient VCC before it releases the reset, and
the time-out delay can be disabled. Disabling the time-out delay without utilizing a brown-out detection circuit is not
recommended.
ATA6612C/ATA6613C [DATASHEET]
47
9111L–AUTO–11/14
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