Figure 5-15. Reset Logic
DATA BUS
MCU Status
Register (MCUSR)
VCC
Power-on Reset
Circuit
BODLEVEL [2..0]
Brown-out
Reset Circuit
Pull-up Resistor
RESET
SPIKE
FILTER
RSTDISBL
Reset Circuit
Watchdog
Timer
Watchdog
Oscillator
Q
S
R
Clock
CK
Generator
Delay Counters
TIMEOUT
CKSEL[3:0]
SUT[1:0]
5.8.3
Power-on Reset
A power-on reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in
Table 5-20 on page 62. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to
trigger the start-up reset, as well as to detect a failure in supply voltage.
A power-on reset (POR) circuit ensures that the device is reset from power-on. Reaching the power-on reset threshold
voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal
is activated again, without any delay, when VCC decreases below the detection level.
ATA6612C/ATA6613C [DATASHEET]
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