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ATA6612C View Datasheet(PDF) - Atmel Corporation

Part Name
Description
MFG CO.
'ATA6612C' PDF : 312 Pages View PDF
5.8.9
Watchdog Timer
Atmel® ATA6612C/ATA6613C has an enhanced watchdog timer (WDT). The main features are:
Clocked from separate on-chip oscillator
3 operating modes
Interrupt
System reset
Interrupt and system reset
Selectable time-out period from 16ms to 8s
Possible hardware fuse watchdog always on (WDTON) for fail-safe mode
Figure 5-21. Watchdog Timer
128kHz
Oscillator
Watchdog
Prescaler
WATCHDOG
RESET
WDE
WDP0
WDP1
WDP2
WDP3
MCU RESET
WDIF
WDIE
INTERRUPT
The watchdog timer (WDT) is a timer counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or
a system reset when the counter reaches a given time-out value. In normal operation mode, it is required that the system
uses the WDR - watchdog timer reset - instruction to restart the counter before the time-out value is reached. If the system
doesn't restart the counter, an interrupt or system reset will be issued.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from
sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations,
giving an interrupt when the operation has run longer than expected. In System Reset mode, the WDT gives a reset when
the timer expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, Interrupt and
system reset mode, combines the other two modes by first giving an interrupt and then switch to system reset mode. This
mode will for instance allow a safe shutdown by saving critical parameters before a system reset.
66 ATA6612C/ATA6613C [DATASHEET]
9111L–AUTO–11/14
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