ATA6612C View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATA6612C
Atmel Corporation
'ATA6612C' PDF : 312 Pages View PDF
Table 5-24. Watchdog Timer Configuration
WDTON
0
0
0
WDE
0
0
1
WDIE
0
1
0
0
1
1
1
x
x
Mode
Stopped
Interrupt mode
System reset mode
Interrupt and system reset mode
System reset mode
Action on Time-out
None
Interrupt
Reset
Interrupt, then go to system reset
Mode
Reset
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler
bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF
must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the
failure.
• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the watchdog timer prescaling when the watchdog timer is running. The different prescaling
values and their corresponding time-out periods are shown in Table 5-25.
Table 5-25. Watchdog Timer Prescale Select
WDP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
WDP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
WDP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
WDP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Number of WDT Oscillator Cycles
2K (2048) cycles
4K (4096) cycles
8K (8192) cycles
16K (16384) cycles
32K (32768) cycles
64K (65536) cycles
128K (131072) cycles
256K (262144) cycles
512K (524288) cycles
1024K (1048576) cycles
Reserved
Typical Time-out at
VCC = 5.0V
16ms
32ms
64ms
0.125s
0.25s
0.5s
1.0s
2.0s
4.0s
8.0s
ATA6612C/ATA6613C [DATASHEET]
69
9111L–AUTO–11/14
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