ATA6617 View Datasheet(PDF) - Atmel Corporation

Part Name

Description

MFG CO.

ATA6617

8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

Atmel Corporation 

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Atmel ATA6616/ATA6617

4.4.2.1

Figure 4-8. Data Memory Map

Data Memory

32 Registers

64 I/O Registers

160 Ext I/O Reg.

0x0000 - 0x001F

0x0020 - 0x005F

0x0060 - 0x00FF

ISRAM start

Internal SRAM

(ISRAM size)

ISRAM end

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clkCPU cycles as described in Figure 4-9.

Figure 4-9. On-chip Data SRAM Access Cycles

T1

T2

T3

clk

CPU

Address

Data

WR

Data

RD

Compute Address

Address valid

4.4.3

Memory Access Instruction

Next Instruction

EEPROM Data Memory

The Atmel® ATtiny87/167 contains EEPROM memory (see “E2 size” in Table 4-3 on page 39).

It is organized as a separate data space, in which single bytes can be read and written. The

EEPROM has an endurance of at least 100,000 write/erase cycles in automotive range. The

access between the EEPROM and the CPU is described in the following, specifying the

EEPROM Address Registers, the EEPROM Data Register and the EEPROM Control

Register.

Section 4.22 “Memory Programming” on page 250 contains a detailed description on

EEPROM programming in SPI or Parallel Programming mode.

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9132D–AUTO–12/10

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