ATF-521P8-BLK View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
ATF-521P8-BLK
Avago Technologies
'ATF-521P8-BLK' PDF : 23 Pages View PDF
Amp
Frequency
Figure 4. High Pass Frequency Response.
The second solution is a low pass configuration with a
shunt capacitor and a series inductor shown in Figure 5
and 6.
RFin L1
RFout
C1
Figure 5. Low Pass Circuit Topology.
Amp
Frequency
Figure 6. Low Pass Frequency Response.
The actual values of these components may be calcu‑
lated by hand on a Smith Chart or more accurately done
on simulation software such as ADS. There are some
advantages and disadvantages of choosing a high pass
versus a low pass. For instance, a high pass circuit cuts
off low frequency gain, which narrows the usable band‑
width of the amplifier, but consequently helps avoid
potential low frequency instability problems. A low pass
match offers a much broader frequency response, but it
has two major disadvantages. First it has the potential
for low frequency instability, and second it creates the
need for an extra DC blocking capacitor on the input
in order to isolate the device gate from the preceding
stages.
Figure 7 displays the input and output matching se‑
lected for ATF-521P8. In this example the input and out‑
put match both essentially function as high pass filters,
but the high frequency gain of the device rolls off pre‑
cipitously giving a narrow band frequency response, yet
still wide enough to accommodate a CDMA or WCDMA
transmit band. For more information on RF matching
techniques refer to MGA-53543 application note.
Passive Bias [1]
Once the RF matching has been established, the next
step is to DC bias the device. A passive biasing example
is shown in Figure 8. In this example the voltage drop
across resistor R3 sets the drain current (Id) and is calcu‑
lated by the following equation:
R3 = Vdd – Vds
(1)
Ids + Ibb p
where,
Vdd is the power supply voltage;
Vds is the device drain to source voltage;
Ids is the device drain to source current;
Ibb for DC stability is 10X the typical gate current;
A voltage divider network with R1 and R2 establishes
the typical gate bias voltage (Vg).
R1 = Vg
(2)
Ip
bb
R2 = (Vdd – Vg) x R1 (3)
Vg
Often the series resistor, R4, is added to enhance the
low frequency stability. The complete passive bias ex‑
ample may be found in reference [1].
RFin C1
Zo
52
C2
C3
Zo
RFout
L1
Input Match
Amp
Amp
+
ATF-521P8
Amp
+
Output Match
Total Response
Amp
=
Frequency
Frequency
Frequency
Frequency
Figure 7. Input and Output Match for ATF‑521P8 at 2 GHz.
15
Share Link: 