ATMEGA161-8PC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATMEGA161-8PC
Atmel Corporation
'ATMEGA161-8PC' PDF : 159 Pages View PDF
Figure 29. Watchdog Reset During Operation
MCU Status Register – MCUSR
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit
$34 ($54)
Read/Write
Initial value
7
6
5
4
3
2
1
0
-
-
-
-
WDRF
BORF
EXTRF
PORF
MCUSR
R
R
R
R
R/W
R/W
R/W
R/W
0
0
0
0
See bit description
• Bits 7..4 - Res: Reserved Bits
These bits are reserved bits in the ATmega161 and always read as zero.
• Bit 3 - WDRF: Watchdog Reset Flag
This bit is set if a watchdog reset occurs. The bit is cleared by a power-on reset, or by writing a logic zero to the flag.
• Bit 2 - BORF: Brown-out Reset Flag
This bit is set if a brown-out reset occurs. The bit is cleared by a power-on reset, or by writing a logic zero to the flag.
• Bit 1 - EXTRF: External Reset Flag
This bit is set if an external reset occurs. The bit is cleared by a power-on reset, or by writing a logic zero to the flag.
• Bit 0 - PORF: Power-on Reset Flag
This bit is set if a power-on reset occurs. The bit is cleared only by writing a logic zero to the flag.
To make use of the reset flags to identify a reset condition, the user should read and then clear the MCUSR as early as
possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by
examining the reset flags.
Interrupt Handling
The ATmega161 has two 8-bit Interrupt Mask control registers; GIMSK – General Interrupt Mask register and TIMSK –
Timer/Counter Interrupt Mask register.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user soft-
ware can set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction –
RETI – is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hard-
ware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set
and remembered until the interrupt is enabled, or the flag is cleared by software.
28
ATmega161(L)
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