ATMEGA161-8PC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATMEGA161-8PC
Atmel Corporation
'ATMEGA161-8PC' PDF : 159 Pages View PDF
ATmega161(L)
If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt
flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is
present.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. After 4 clock cycles the
program vector address for the actual interrupt handling routine is executed. During this 4 clock cycle period, the Program
Counter (13 bits) is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes
3 clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the
interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by 4 clock cycles.
A return from an interrupt handling routine takes 4 clock cycles. During these 4 clock cycles, the Program Counter (2 bytes)
is popped back from the Stack, the Stack Pointer is incremented by 2, and the I flag in SREG is set. When AVR exits from
an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is
served.
General Interrupt Mask Register – GIMSK
Bit
7
6
5
4
$3B ($5B)
INT1
INT0
INT2
-
Read/Write
R/W
R/W
R
R
Initial value
0
0
0
0
3
2
1
0
-
-
-
-
GIMSK
R
R
R
R
0
0
0
0
• Bit 7 - INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) define whether
the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause
an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is
executed from program memory address $004. See also “External Interrupts”.
• Bit 6 - INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether
the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause
an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is
executed from program memory address $002. See also “External Interrupts.”
• Bit 5- INT2: External Interrupt Request 2 Enable
When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated.
The Interrupt Sense Control2 bit (ISC02 in the Extended MCU Control Register (EMCUCR) defines whether the external
interrupt is activated on rising or falling edge of the INT2 pin. Activity on the pin will cause an interrupt request even if INT2
is configured as an output. The corresponding interrupt of External Interrupt Request 2 is executed from program memory
address $006. See also “External Interrupts.”
• Bits 4..0 - Res: Reserved bits
These bits are reserved bits in the ATmega161 and always read as zero.
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