ATMEGA64RZAV-10PU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATMEGA64RZAV-10PU
Atmel Corporation
'ATMEGA64RZAV-10PU' PDF : 377 Pages View PDF
ATmega644
6.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clkCPU cycles as described in Figure 6-3.
Figure 6-3. On-chip Data SRAM Access Cycles
T1
T2
T3
clk
CPU
Address
Data
WR
Data
RD
Compute Address
Address valid
Memory Access Instruction
Next Instruction
6.3 EEPROM Data Memory
6.3.1
The ATmega644 contains 2 Kbytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
page 299, page 303, and page 287 respectively.
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 6-2. A self-timing function, however,
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See Section “6.3.2” on page 20. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
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2593O–AVR–02/12
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