ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
13.5.28 L2CC Prefetch Control Register
Name:
L2CC_PCR
Address: 0x00A00F60
Access: Read/Write in Secure mode
Read-only in Non-secure mode
31
30
29
28
27
26
–
DLEN
INSPEN
DATPEN
DLFWRDIS
–
25
24
–
PDEN
23
22
21
20
19
18
17
16
IDLEN
–
NSIDEN
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
OFFSET
• OFFSET: Prefetch Offset
You must only use the Prefetch offset values of 0-7, 15, 23, and 31 for these bits. The L2CC does not support the other
values.
• NSIDEN: Not Same ID on Exclusive Sequence Enable
0: Read and write portions of a non-cacheable exclusive sequence have the same AXI ID when issued to L3. This is the
default value.
1: Read and write portions of a non-cacheable exclusive sequence do not have the same AXI ID when issued to L3.
• IDLEN: INCR Double Linefill Enable
0: The L2CC does not issue INCR 8x64-bit read bursts to L3 on reads that miss in the L2 cache. This is the default value.
1: The L2CC can issue INCR 8x64-bit read bursts to L3 on reads that miss in the L2 cache.
Note: This bit can only be used if the DLEN bit is set HIGH. Refer to Section 13.4.1 “Double Linefill Issuing” for details on double linefill
functionality.
• PDEN: Prefetch Drop Enable
0: The L2CC does not discard prefetch reads issued to L3. This is the default value.
1: The L2CC discards prefetch reads issued to L3 when there is a resource conflict with explicit reads.
• DLFWRDIS: Double Linefill on WRAP Read Disable
0: Double linefill on WRAP read is enabled. This is the default value.
1: Double linefill on WRAP read is disabled.
Note: This bit can only be used if the DLEN bit is set HIGH. Refer to Section 13.4.1 “Double Linefill Issuing” for details on double linefill
functionality.
• DATPEN: Data Prefetch Enable
0: Data prefetching is disabled. This is the default value.
1: Data prefetching is enabled.
SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
119
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