ATSGA204A View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'ATSGA204A' PDF : 93 Pages View PDF
ATSHA204A
I2C Interface
6. I2C Interface
The I2C interface uses the SDA and SCL pins to indicate various I/O states to the ATSHA204A. This
interface is designed to be compatible at the protocol level with other I2C devices operating up to 1 MHz.
The SDA pin must be pulled high with an external pull-up resistor, as the ATSHA204A includes only an
open-drain driver on its output pin. The bus master may be either open-drain or totem pole and if the
latter, then it should be tri-stated when the ATSHA204A is driving results on the bus. The SCL pin is an
input and must be driven both high and low at all times by an external device or pull-up.
6.1
6.1.1
6.1.2
I/O Conditions
The ATSHA204A device responds to the following I/O conditions outlined in the Device is Asleep and
Device is Awake sections.
Device is Asleep
When the device is asleep, it ignores all but the Wake condition.
• Wake: If SDA is held low for a period greater than tWLO, the device exits low-power mode and, after
a delay of tWHI, is ready to receive I2C commands. The device ignores any levels or transitions on
the SCL pin when the device is idle or asleep and during tWLO. At some point during tWHI, the SCL
pin is enabled and the conditions listed in Section Device is Awake, are honored.
The Wake condition requires that either the system processor manually drives the SDA pin low for tWLO,
or that a data byte of 0x00 is transmitted at a clock rate sufficiently slow so that SDA is low for a
minimum period of tWLO. When the device is awake, the normal processor I2C hardware and/or software
can be used for device communications up to and including the I/O sequence required to put the device
back into low-power (for example sleep) mode.
When there are multiple ATSHA204A devices on the bus and the I2C interface is run at 133 KHz or
slower, the transmission of certain data patterns (such as 0x00) causes all the ATSHA204A devices on
the bus to wake-up. Because subsequent device addresses transmitted along the bus can only match the
desired devices, the unused devices remain inactive and do not cause any bus conflicts.
In I2C mode, the device ignores a wake sequence that is sent when the device is already awake.
Device is Awake
When the device is awake, it honors the conditions listed below:
• Data Zero: if SDA is low and stable while SCL goes from low to high to low, then a zero bit is being
transferred on the bus. SDA can change while SCL is low.
• Data One: if SDA is high and stable while SCL goes from low to high to low, then a one bit is being
transferred on the bus. SDA can change while SCL is low.
© 2018 Microchip Technology Inc.
DS40002025A-page 28
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