C8051F067 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F067' PDF : 328 Pages View PDF
C8051F060/1/2/3/4/5/6/7
1.3. JTAG Debug and Boundary Scan
The C8051F06x family has on-chip JTAG boundary scan and debug circuitry that provides non-intrusive,
full speed, in-circuit debugging using the production part installed in the end application, via the four-pin
JTAG interface. The JTAG port is fully compliant to IEEE 1149.1, providing full boundary scan for test and
manufacturing purposes.
Silicon Laboratories' debugging system supports inspection and modification of memory and registers,
breakpoints, watchpoints, a stack monitor, and single stepping. No additional target RAM, program mem-
ory, timers, or communications channels are required. All the digital and analog peripherals are functional
and work correctly while debugging. All the peripherals (except for the ADCs and SMBus) are stalled when
the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized with
instruction execution.
The C8051F060DK development kit provides all the hardware and software necessary to develop applica-
tion code and perform in-circuit debugging with the C8051F06x MCUs. The kit includes a Windows (95 or
later) development environment, a serial adapter for connecting to the JTAG port, and a target application
board with a C8051F060 MCU installed. All of the necessary communication cables and a wall-mount
power supply are also supplied with the development kit. Silicon Labs’ debug environment is a vastly supe-
rior configuration for developing and debugging embedded applications compared to standard MCU emu-
lators, which use on-board "ICE Chips" and target cables and require the MCU in the application board to
be socketed. Silicon Labs' debug environment both increases ease of use and preserves the performance
of the precision, on-chip analog peripherals.
WINDOWS 95 OR LATER
Silicon Labs Integrated
Development Environment
Serial
Adapter
JTAG (x4), VDD, GND
TARGET PCB
C8051
F060
Figure 1.8. Development/In-System Debug Diagram
28
Rev. 1.2
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