C8051F067 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F067' PDF : 328 Pages View PDF
C8051F060/1/2/3/4/5/6/7
1.4. Programmable Digital I/O and Crossbar
Three standard 8051 Ports (0, 1, and 2) are available on the MCUs. The C8051F060/2/4/6 have 4 addi-
tional 8-bit ports (3, 5, 6, and 7), and a 3-bit port (port 4) for a total of 59 general-purpose I/O Pins. The
Ports behave like the standard 8051 with a few enhancements.
Each port pin can be configured as either a push-pull or open-drain output. Also, the "weak pull-ups" which
are normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for
low-power applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is a large digital switching network that
allows mapping of internal digital system resources to Port I/O pins on P0, P1, P2, and P3.
(See Figure 1.9) Unlike microcontrollers with standard multiplexed digital I/O ports, all combinations of
functions are supported with all package options offered.
The on-chip counter/timers, serial buses, HW interrupts, comparator outputs, and other digital signals in
the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers.
This allows the user to select the exact mix of general purpose Port I/O and digital resources needed for
the particular application.
Highest
Priority
Lowest
Priority
UART0
2
4
SPI
2
SMBus
2
UART1
6
PCA
Comptr.
2
Outputs
T0, T1, T2,
T2EX, T3,
T3EX,
8
T4,T4EX,
/INT0,
/INT1
/SYSCLK
CNVSTR2
Port
Latches
8
P0 (P0.0-P0.7)
8
P1 (P1.0-P1.7)
8
P2 (P2.0-P2.7)
8
P3 (P3.0-P3.7)
XBR0, XBR1, XBR2,
XBR3 P1MDIN,
P2MDIN, P3MDIN
Registers
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
Priority
Decoder
8
P0
I/O
Cells
Digital
Crossba 8
P1
r
I/O
Cells
External
Pins
P0.0
P0.7
Highest
Priority
P1.0
P1.7
8
P2
P2.0
I/O
Cells
P2.7
8
P3
I/O
Cells
To ADC2 Input
(C8051F060/1/2/3)
To Comparators
P3.0
P3.7
C8051F060/2/4/6
Only
Lowest
Priority
Figure 1.9. Digital Crossbar Diagram
Rev. 1.2
29
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