C8051F327 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
'C8051F327' PDF : 141 Pages View PDF
C8051F326/7
SFR Definition 6.9. EIE1: Extended Interrupt Enable 1
R
R
R
R
R
R
—
—
—
—
—
—
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit7–2:
Bit1:
Bit0:
Unused. Read = 000000b. Write = don’t care.
EUSB0: Enable USB0 Interrupt.
This bit sets the masking of the USB0 interrupt.
0: Disable all USB0 interrupts.
1: Enable interrupt requests generated by USB0.
Unused. Read = 0. Write = don’t care.
R/W
EUSB0
Bit1
R
Reset Value
— 00000000
Bit0 SFR Address:
0xE6
SFR Definition 6.10. EIP1: Extended Interrupt Priority 1
R
R
R
R
R
R
—
—
—
—
—
—
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit7–2:
Bit1:
Bit0:
Unused. Read = 000000b. Write = don’t care.
PUSB0: USB0 Interrupt Priority Control.
This bit sets the priority of the USB0 interrupt.
0: USB0 interrupt set to low priority level.
1: USB0 interrupt set to high priority level.
Unused. Read = 0. Write = don’t care.
R/W
PUSB0
Bit1
R
Reset Value
— 00000000
Bit0 SFR Address:
0xF6
SFR Definition 6.11. EIE2: Extended Interrupt Enable 2
R
R
R
R
R
R
R
—
—
—
—
—
—
—
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bits7–1:
Bit0:
Unused. Read = 0000000b. Write = don’t care.
EVBUS: Enable VBUS Level Interrupt.
This bit sets the masking of the VBUS interrupt.
0: Disable all VBUS interrupts.
1: Enable interrupt requests generated by VBUS level sense.
R/W
EVBUS
Bit0
Reset Value
00000000
SFR Address:
0xE7
Rev. 1.1
53
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