C8051F902-GD View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
C8051F902-GD
Silicon Laboratories
'C8051F902-GD' PDF : 318 Pages View PDF
C8051F91x-C8051F90x
Figure 3.4. Typical QFN-24 Landing Diagram
Table 3.3. PCB Land Pattern
Dimension
C1
C2
E
Notes:
Min
Max
3.90
4.00
3.90
4.00
0.50 BSC
Dimension
Min
Max
X1
0.20
0.30
X2
2.70
2.80
Y1
0.65
0.75
Y
2.70
2.80
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 2 x 2 array of 1.0 x 1.0 mm square openings on 1.30 mm pitch should be used for the
center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Rev. 1.0
33
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