C8051F902-GD View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F902-GD

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

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C8051F91x-C8051F90x

Figure 3.6. QSOP-24 Landing Diagram

Table 3.5. PCB Land Pattern

Dimension

MIN

C

5.20

MAX

5.30

E

0.635 BSC

X

Y

Notes:

General

0.30

0.40

1.50

1.60

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This land pattern is based on the IPC-7351 guidelines.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NMSD). Clearance between the solder mask and

the metal pad is to be 60 m minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to

assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.

Card Assembly

1. A No-Clean, Type 3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Components.

Rev. 1.0

35

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