C8051F902-GD View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
C8051F902-GD
Silicon Laboratories
'C8051F902-GD' PDF : 318 Pages View PDF
C8051F91x-C8051F90x
Table 4.2. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter
Conditions
Min Typ Max Units
Notes:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained
with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration
requires 3 CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary slightly
based on the physical location of the sjmp instruction and the number of Flash address lines that toggle as a
result. In the worst case, current can increase by up to 30% if the sjmp loop straddles a 64-byte Flash address
boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have
few transitions across the 64-byte address boundaries.
4. Includes oscillator and regulator supply current.
5. IDD can be estimated for frequencies <14 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range, then adding an offset of 90 µA. When using these numbers to
estimate IDD for >14 MHz, the estimate should be the current at 25 MHz minus the difference in current
indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 4 mA –
(25 MHz – 20 MHz) x 0.102 mA/MHz = 3.5 mA assuming the same oscillator setting.
6. The supply current specifications in Table 4.2 are for two cell mode. The VBAT current in one-cell mode can
be estimated using the following equation:
VBAT Current (one-cell mode) = --S----u-D--p--C--p----l-D-y----CV----o--C--l-t-o-a--n-g---ve---e---r--t--eS---r-u---Ep----pf-f--li-yc---i--eC---n-u--c--r-y-r--e---n---t-V---(-B-t-w--A---o-T-----c-V--e--o-l--ll--t-ma----g-o--e-d---e----)
The VBAT Voltage is the voltage at the VBAT pin, typically 0.9 to 1.8 V.
The Supply Current (two-cell mode) is the data sheet specification for supply current.
The Supply Voltage is the voltage at the VDD/DC+ pin, typically 1.8 to 3.3 V (default = 1.9 V).
The DC-DC Converter Efficiency can be estimated using Figure 4.3–Figure 4.5.
7. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the
frequency sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 2.1 mA – (25 MHz –
5 MHz) x 0.079 mA/MHz = 0.52 mA.
8. Internal LFO only available on ‘F912 and ‘F902 devices.
9. Ability to disable VBAT supply monitor only available on ‘F912 and ‘F902 devices.
40
Rev. 1.0
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