GPx_OUT
GPx_EN
GPx_DAT
GPx_nIOW
GPx_nIOR
DQ
D-TYPE
CLK
1
QD
TRANS-
0
PARENT
G
GPIOx
FIGURE 7 - GENERAL PURPOSE I/O BLOCK DIAGRAM
Note: This figure is for illustration purposes only and is not intended to suggest specific
implementation details)
Registers
I/O pin is disabled. The affects of the GPx_EN
GPIOA Enable Register
bits are summarized in TABLE 30. GP00 can be
accessed both in the configuration state and the
The GPIOA Enable register GP00 contains the
enable bits for the five general purpose I/O pins
(TABLE 31). When any of the GPx_EN bits are
“1”, the associated general purpose I/O pin is
enabled. When any of the GPx_EN bits are “0”,
run state (see section REGISTER ADDRESS
MAP on page 16 and TABLE 29). The default
value of the GPIOA Enable register after power
up is 00H. Bits[7:5] in the GPIOA Enable
register are RESERVED.
the
associated
general
purpose
GP00 R/W
TABLE 31 - GPIOA ENABLE REGISTER
D7 D6 D5 D4
D3
D2
D1
GP4_ GP3_ GP2_ GP1_
RESERVED
EN
EN
EN
EN
D0
GP0_
EN
DEFAULT
0x00
34