CC1110Fx / CC1111Fx
Byte Bit
Offset
7
5:4
7
3
7
2
7
1:0
Field Name
Description
DESTINC[1:0]
Destination address increment mode (after each transfer)
00
0 bytes/words
01
1 bytes/words
10
2 bytes/words
11
-1 bytes/words
IRQMASK
Interrupt Mask for this channel.
0
Disable interrupt generation
1
Enable interrupt generation upon DMA channel done
M8
Mode of 8th bit in transfer count for variable length transfers (VLEN≠000 and
VLEN≠111). Only applicable when WORDSIZE=0.
0 Use all 8 bits for transfer count
1 Use 7 LSB for transfer count
PRIORITY[1:0]
The DMA channel priority:
00
Low, DMA access will always defer to a CPU access
01
Normal, guarantees that DMA access prevails over CPU on at least every
second try.
10
High, DMA access will always prevail over CPU access.
11
Reserved
Table 52: DMA Configuration Data Structure
SWRS033E
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