CC1111F16RSPR View Datasheet(PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
Part Name
Description
MFG CO.
CC1111F16RSPR
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
'CC1111F16RSPR' PDF : 240 Pages View PDF
CC1110Fx / CC1111Fx
13.5.8 DMA Registers
This section describes the SFRs associated with the DMA Controller.
DMAARM (0xD6) – DMA Channel Arm
Bit Name
Reset
7
ABORT
0
R/W
R0/W
6:5
4
DMAARM4
3
DMAARM3
2
DMAARM2
1
DMAARM1
0
DMAARM0
0
R0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
DMA abort. Ongoing DMA transfer or armed DMA channels
will be aborted when writing a 1 to this bit, and at the same
time select which DMA channels to abort by setting the
corresponding, DMAARM.DMAARMn bits to 1
0 Normal operation
1 Abort channels all selected channels
Not used
DMA arm channel 4
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
DMA arm channel 3
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
DMA arm channel 2
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
DMA arm channel 1
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
DMA arm channel 0
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
SWRS033E
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