CC1111F16RSPR View Datasheet(PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
Part Name
Description
MFG CO.
CC1111F16RSPR
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
'CC1111F16RSPR' PDF : 240 Pages View PDF
new interrupt request if the corresponding
interrupt flag is set.
When the timer is used in Free-running Mode
or Modulo Mode the interrupt flags are set as
follows:
• T1CTL.CH0IF, T1CTL.CH1IF, and
T1CTL.CH2IF
are set on
compare/capture event
• T1CTL.OVFIF is set when counter
reaches terminal count value (overflow)
When the timer is used in Up/Down Mode the
interrupt flags are set as follows:
In compare mode:
• T1CTL.CH0IF and T1CTL.OVFIF
are set when counter turns around on
zero
• T1CTL.CH1IF and T1CTL.CH2IF
are set on compare event
In capture mode:
• T1CTL.OVFIF is set when counter
turns around on zero
• T1CTL.CH0IF, T1CTL.CH1IF, and
T1CTL.CH2IF are set on capture event
I addition, the CPU interrupt flag, IRCON.T1IF
will be asserted if the channel n interrupt mask
bit (T1CCTLn.IM) is set to 1.
13.6.7 Timer 1 DMA Triggers
There are three DMA triggers associated with
Timer 1, one for each channel. These are DMA
triggers T1_CH0, T1_CH1 and T1_CH2, which
are generated on timer capture/compare
events as follows:
• T1_CH0 - Channel 0 capture/compare
• T1_CH1 - Channel 1 capture/compare
• T1_CH2 - Channel 2 capture/compare
13.6.8 DSM Mode
Timer 1 also contains a 1-bit Delta-Sigma
Modulator (DSM) of second order that can be
used to produce a mono audio output PWM
signal. The DSM removes the need for high
order external filtering required when using
regular PWM mode.
The DSM operates at a fixed speed of either
1/4 or 1/8 of the timer tick speed set by
CLKCON.TICKSPD. The DSM speed is set by
T1CCTL1.MODE. The input samples are
updated at a configurable sampling rate set by
the terminal count value T1CC0.
An interpolator is used to match the sampling
rate with the DSM update rate. This
CC1110Fx / CC1111Fx
interpolator is of first order with a scaling
compensation. The scaling compensation is
due to variable gain defined by the difference
in sampling speed and DSM speed. This
interpolation mechanism can be disabled by
setting
T1CCTL1.CAP=10
or
T1CCTL1.CAP=11, thus using a zeroth order
interpolator.
In addition to the interpolator, a shaper can be
used to account for differences in rise/fall times
in the output signal. Also the shaper is
enabled/disabled using the two CAP bits in the
T1CCTL1 register. This shaper ensures a
rising and a falling edge per bit and will thus
limit the output swing to 1/8 to 7/8 of I/O VDD
when the DSM operates at 1/8 of the timer tick
speed or 1/4 to 3/4 of I/O VDD when the DSM
operates at 1/4 of the timer tick speed.
The DSM is used as in PWM mode where the
terminal count value T1CC0 defines the
period/sampling rate. The DSM can not use
the Timer 1 prescaler to further slow down the
period.
Timer 1 must be configured to operate in
modulo mode (T1CTL.MODE=10) and channel
0 must be configured to compare mode
(T1CCTL0.MODE=1). The terminal count
value T1CC0, held in the registers
T1CC0H:T1CC0L, defines the sample rate.
Table 53 shows some T1CC0 settings for
different
sample
rates
(CLKCON.TICKSPD=000).
Sample Rate
T1CC0H T1CC0L
8 kHz @ 24 MHz 0x0B
0xB7
8 kHz @ 26 MHz 0x0C
0xB1
16 kHz @ 24 MHz 0x05
0xDB
16 kHz @ 26 MHz 0x06
0x59
48 kHz @ 24 MHz 0x01
0xF3
48 kHz @ 26 MHz 0x02
0x1D
64 kHz @ 24 MHz 0x01
0x76
64 kHz @ 26 MHz 0x01
0x96
Table 53: Channel 0 Period Setting for some
Sampling Rates (CLKCON.TICKSPD=000)
Since the DSM starts immediately after DSM
mode has been enabled by setting
T1CCTL1.CMP=111, all configuration should
have been performed prior to enabling DSM
mode. Also, the Timer 1 counter should be
cleared and started just before starting the
DSM operation (all write accesses to the
T1CNTL register will reset the 16-bit counter
while writing a value other than 00 to
T1CTL.MODE will start the counter). A simple
SWRS033E
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