CDH2D09 View Datasheet(PDF) - Maxim Integrated
Part Name
Description
MFG CO.
'CDH2D09' PDF : 44 Pages View PDF
PMIC with Integrated Charger and
Smart Power Selector for Handheld Devices
Pin Description
PIN
NAME
FUNCTION
1
USUS
USB Suspend Digital Input. As shown in Table 1, driving USUS high suspends the DC or USB inputs
if they are configured as a USB power input.
2
DC
DC Power Input. DC is capable of delivering 1A to SYS. DC supports both AC adaptors and USB
inputs. As shown in Table 1, the DC current limit is controlled by PEN1, PEN2, USUS, and RDISET.
3
USB
USB Power Input. USB is capable of delivering 0.5A to SYS. As shown in Table 1, the USB current
limit is controlled by PEN1, PEN2, and USUS.
4
FB5
Feedback Input for REG5. Connect FB5 to the center of a resistor voltage-divider from OUT5 to
AGND to set the REG5 output voltage from 0.6V to VPV5.
5
PV5
Power Input for REG5. Connect PV5 to SYS, or a supply between 1.7V and VSYS. Bypass PV5 to
power ground with a 1µF ceramic capacitor.
6
OUT5 Linear Regulator Power Output. OUT5 is internally pulled to AGND by 1kΩ in shutdown.
7
PG2
Power Ground for the REG2 Step-Down Regulator
8
LX2
Inductor Switching Node for REG2. LX2 is internally pulled to PG2 by 1kΩ in shutdown.
9
PV2
Power Input for the REG2 Step-Down Regulator. Connect PV2 to SYS. Bypass PV2 to PG2 with a
4.7µF ceramic capacitor.
10
CEN
Active-Low Charger Enable Input. Pull CEN low to enable the charger, or drive CEN high to disable
charging. The battery charger is also disabled when USUS is high.
11
FB2
Feedback Input for REG2. Connect FB2 to the center of a resistor voltage-divider from the REG2
output capacitors to AGND to set the output voltage from 1V to VSYS.
12
DOK
Active-Low, Open-Drain DC Power-OK Output. DOK is low when VDC is within its valid operating
range.
13
FB4
Feedback Input for REG4. Connect FB4 to the center of a resistor voltage-divider from the REG4
output capacitors to AGND to set the output voltage from 0.6V to VPV4.
14
BP
Reference Noise Bypass. Bypass BP with a low-leakage 0.01µF ceramic capacitor for reduced noise
on the LDO outputs.
15
OUT4 Linear Regulator Power Output. OUT4 is internally pulled to AGND in shutdown.
16
PV4
Power Input for REG4. Connect PV4 to SYS, or a supply between 1.7V and VSYS. Bypass PV4 to
power ground with a 1µF ceramic capacitor.
Battery Regulation Voltage Set Node. Drive BVSET low to set the regulation voltage to 4.1V. Connect
17
BVSET BVSET to VL or leave unconnected to set the regulation voltage to 4.2V. Connect BVSET to AGND
through a 50kΩ resistor to set the regulation voltage to 4.350V.
18
AGND Ground. AGND is the low-noise ground connection for the internal circuitry.
19
FB1
Feedback Input for REG1. Connect FB1 to the center of a resistor voltage-divider from the REG1
output capacitors to AGND to set the output voltage from 1V to VSYS.
20
EN
Regulator Enable Input. Drive EN high to enable all regulator outputs. The sequencing is shown in
Figure 11. Drive EN low to disable the regulators.
Forced-PWM Input. Connect PWM high for forced-PWM operation on REG1, REG2, and REG3.
21
PWM
Connect PWM low for auto PWM operation. Do not change PWM on-the-fly. See the PWM section
for more information.
22
PV1
Power Input for the REG1 Step-Down Regulator. Connect PV1 to SYS. Bypass PV1 to PG1 with a
4.7µF ceramic capacitor.
20 ______________________________________________________________________________________
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